1. Field of the invention
The present invention relates to a multiport RAM in which the read/write operation is capable even if one clock signal for deciding a read timing has no relation with another clock signal for deciding a write timing in the frequency and synchronization and an information processing unit in which data are transmitted through the multiport RAM between two apparatuses.
2. Description of the Background Art
In general, the operation that a data provided from an apparatus A is once memorized in a multiport RAM and the memorized data is read out and provided to an apparatus B is often carried out when the data transmission is carried out between the apparatus A and the apparatus B in the information processing unit.
For example, a conventional structure for carrying out the above mentioned data transmission is explained with reference to FIG. 1 as follows.
FIG. 1 shows that a data memorized in one apparatus A operated by a clock signal CK1 is transmitted to another apparatus B operated by a clock signal CK2 having no relation with the signal CK1 and is memorized into a dual port RAM 1 to use the data for the processing in the apparatus B. Also, FIGS. 2A and 2B shows a timing chart of the signals shown in FIG. 1.
As shown in FIG. 1, the apparatus A is provided with a register RA for providing a 16 bits data to the apparatus B in synchronization with the clock signal CK1. Also the apparatus B is provided with the dual port RAM 1 formed of a 32 bit by 16 word array as a register file. The dual port RAM 1 processes a 32 bit data in synchronization with the clock signal CK2 which is formed by demultiplying the clock signal CK1 to a half frequency in a frequency divider 2. In other words, the 32 bit data which is 2 times as wide as the 16 bit data in the apparatus A is processed in a half processing speed in comparison with a processing speed in the apparatus A.
To match the timing in the data transmission between the apparatus A and the apparatus B, the apparatus B is also provided with buffer registers R1 and R2 in parallel with each other for matching the data width and the operational timing. The 16 bit data, which are memorized into the register RA and are provided to the buffer register R1, R2 by turns in synchronization with the clock signal CK1.
In addition, the apparatus B is provided with a control section 3 for controlling the 16 bit data transmission from the buffer register R1 and R2 to the dual port RAM 1 and the 32 bit data transmission from the dual port RAM 1 to the apparatus B. The control section provides a write signal W1 synchronized with the clock signal CK2 to the buffer register R1 and also provides an inverted signal W2 of the write signal W1 to the buffer register R2. Therefore, the first prescribed 16 bit data D1 memorized in the register RA is at first provided to the buffer register R1 in synchronization with a leading edge of the write signal W1. And then the write operation is completed in synchronization with the first trailing edge of the write signal W1 after the leading edge while the second 16 bits data D2 memorized in the register RA is provided to the buffer register R2 in synchronization with the leading edge of the inverted write signal W2.
The data respectively memorized in buffer registers R1 and R2 are read out in synchronization with the write signal W1 and the inverted write signal W2 in turn and are coupled with each other to make up the 32 bit data provided to the input port of the dual port RAM 1. Thereafter the 32 bit data is memorized in the dual port RAM 1 in synchronization with the clock signal CK2 and under control of a read enable signal RE and a read address signal RA to use for the processing in the apparatus B.
However, elements such as the buffer registers R1 and R2 for constructing the above mentioned system are necessary to match the timing of the data transmission when the data transmission is carried out through the dual port RAM 1 between the apparatuses A, B which are respectively operated in accordance with the clock signals CK1, CK2 having no relation with each other.
FIG. 3 is a block diagram similar to FIG. 1, showing another conventional system in which the data transmission is carried out through the dual port RAM 1 between the apparatuses A and B which are respectively operated in accordance with clock signals CKA, CKB having the same frequency and no synchronization with each other. Also FIG. 4 and FIG. 5 are respectively a timing chart of the signals shown in FIG. 3.
As shown in FIG. 3, a 32 bit data memorized in a register RA of the apparatus A is transmitted to the apparatus B. To match the timing in the data transmission between apparatuses A and B, the apparatus B is provided with prebuffers PB1, PB2 in series with each other in the upstream of the dual port RAM 1 and the data transmission is carried out in a so-called hand shaking method.
In the apparatus A, a write go signal WG for requesting the write operation to the prebuffer PB1 is provided to a control section 5 in the apparatus B from a control section 6 in the apparatus A in synchronization with a leading edge of the clock signal CKA to transmit the 32 bit data memorized in a register RA to the apparatus B.
In the control section 5, the write go signal WG is sampled in synchronization with a leading edge timing T1 of a high frequency clock signal CKB4, which has a frequency 4 times the frequency of clock signal CKA or CKB, to detect a phase shift between the clock signals CKA and CKB. Then a write signal W1 is provided to the prebuffer PB1 when the output of the write go signal WG is detected.
In the prebuffer PB 1, the 32 bit data D1 is taken out from the register RA in synchronization with a leading edge timing T2 of the next pulse in the clock signal CKB4 in accordance with the write go signal W1. Also, an acknowledge signal AK is provided to the control section A from the control section B to stop the output of the write go signal WG in a prescribed timing after the write signal W1 is provided to the prebuffer PB1 from the control section 5. A write enable signal WE is provided to the dual port RAM 1 from the control section 5 in a prescribed timing after the write signal W1 is provided to the prebuffer PB1. Therefore, the data D1 is provided to the prebuffer PB2 after holding in the prebuffer PB1 to be provided to the input port of the dual port RAM 1 in synchronization with the clock signal CKB, and then the data D1 is memorized in the dual port RAM 1 in accordance with a write address signal WA provided from the control section 5.
The timing that the write enable signal WE is provided to the dual port RAM 1 is changeable in accordance with the timing that the write go signal WG is sampled and detected so that two kinds of the timing that the write go signal WG is sampled and detected are shown in FIG. 4 and FIG. 5. In FIG. 4, the write go signal WG is sampled at the first leading edge timing of the clock signal CKB4 occurred after a leading edge timing of the clock signal CKB. On the other hand, the write go signal WG is sampled at the third leading edge timing of the clock signal CKB4 occurred after a leading edge timing of the clock signal CKB in FIG. 5.
Accordingly, when the data transmission is carried out through the dual port RAM 1 between the apparatuses A and B respectively operated by the clock signals CKA and CKB having no relation with each other, elements such as the prebuffers PB1, PB2 for constructing the above mentioned system are necessary to match the timing of the data transmission even if the data in the apparatus A has the same bit number with the data in the apparatus B.
As mentioned above, the elements such as buffers are necessary to match the timing of the data transmission in an inlet of a multiport RAM when the data transmission is carried out through the multiport RAM between the apparatuses respectively operated by the clock signals having no relation with each other. This means that the timing of the output processing depends on the timing of the input processing in the multiport RAM. In other words, it is impossible to control the input processing (the write operation) and the output processing (the read operation) independently each other because the timing of the input/output can not set up freely.
Accordingly, in the information processing unit in which the multiport RAM is used for a so-called pipeline processing as a register file, the stage number of the pipeline processing is increased by the number of the elements added for matching the timing of the data transmission. Therefore, the structure of the system is in a large scale while the processing speed is lowered, and the design for matching the timing is complicated.
Therefore, the conventional multiport RAM controlled the input/output processing by a single clock signal is not suitable for the data transmission in the information processing unit mentioned above.